The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2021
Filed:
Jan. 16, 2019
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01L 21/56 (2006.01); H01L 23/66 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3114 (2013.01); H01L 23/3135 (2013.01); H01L 23/48 (2013.01); H01L 23/66 (2013.01); H01L 24/02 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68377 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02381 (2013.01);
Abstract
A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.