The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2021
Filed:
Dec. 13, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jayanth N. Rao, Folsom, CA (US);
Murali Sundaresan, Sunnyvale, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G06F 12/00 (2006.01); G06F 12/109 (2016.01); G06T 1/60 (2006.01); G06F 12/0811 (2016.01); G06T 1/20 (2006.01); G06F 12/1036 (2016.01); G06F 12/1081 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 12/00 (2013.01); G06F 12/0811 (2013.01); G06F 12/109 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06F 12/1036 (2013.01); G06F 12/1081 (2013.01); G06F 2212/455 (2013.01); G06F 2212/6042 (2013.01); G06F 2212/62 (2013.01); G06F 2212/656 (2013.01); Y02D 10/00 (2018.01);
Abstract
A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.