The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10928740 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 23, 2021

Filed:

Dec. 04, 2017
Applicant:

Kla-tencor Corporation, Milpitas, CA (US);

Inventors:

Philip Measor, San Jose, CA (US);

Robert M. Danen, San Jose, CA (US);

Assignee:

KLA Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01); G03F 7/00 (2006.01); G03F 1/84 (2012.01); H01J 37/28 (2006.01); G01N 21/95 (2006.01); H01L 21/67 (2006.01); H01L 21/66 (2006.01); G01N 21/93 (2006.01); G01N 21/956 (2006.01);
U.S. Cl.
CPC ...
G03F 7/7065 (2013.01); G01N 21/93 (2013.01); G01N 21/9501 (2013.01); G01N 21/9503 (2013.01); G01N 21/95607 (2013.01); G03F 1/84 (2013.01); G03F 7/0037 (2013.01); H01J 37/28 (2013.01); H01L 22/12 (2013.01); H01L 22/26 (2013.01); H01J 2237/2817 (2013.01); H01L 21/67288 (2013.01);
Abstract

A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) including one or more programmed surface defects. The three-dimensional calibration structure includes a planarized layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on the planarized layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. One or more air gaps are formed in the layer stack following deposition of the cap layer. The three-dimensional calibration structure includes one or more holes formed into at least one of the cap layer, the layer stack, or the planarized layer.


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Measor, Philip. (2021). Three-dimensional calibration structures and methods for measuring buried defects on a three-dimensional semiconductor wafer (U.S. Patent No. 10928740). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10928740

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