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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10923494 B1

PDFFull Text
Date of Patent:
Feb. 16, 2021

Filed:

Nov. 19, 2018

Electronic devices comprising a source below memory cells and related systems

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Darwin A. Clampitt, Wilder, ID (US);

David H. Wells, Boise, ID (US);

John D. Hopkins, Meridian, ID (US);

Kevin Y. Titus, Nampa, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

TraskBritt

Primary Examiner:

Sonya McCall-Shepard

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11521 (2017.01); H01L 29/08 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/11568 (2017.01); H01L 27/11556 (2017.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/45 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0228 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/66545 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02576 (2013.01); H01L 21/3212 (2013.01); H01L 29/456 (2013.01); H01L 29/665 (2013.01);
Abstract

A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.

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