The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Aug. 21, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Takeshi Iwamoto, Tokyo, JP;

Kazushi Kono, Tokyo, JP;

Masashi Arakawa, Tokyo, JP;

Toshiaki Yonezu, Tokyo, JP;

Shigeki Obayashi, Tokyo, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 23/62 (2006.01); H01L 23/525 (2006.01); H01L 23/528 (2006.01); H01H 85/041 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5256 (2013.01); H01H 85/041 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 23/53228 (2013.01); H01L 23/53238 (2013.01); H01L 23/525 (2013.01); H01L 23/5227 (2013.01); H01L 23/62 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.


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