The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Oct. 26, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andrew Greene, Albany, NY (US);

Marc Bergendahl, Rensselaer, NY (US);

Ekmini A. De Silva, Slingerlands, NY (US);

Alex Joseph Varghese, Ballston Lake, NY (US);

Yann Mignot, Slingerlands, NY (US);

Matthew T. Shoudy, Guilderland, NY (US);

Gangadhara Raja Muthinti, Albany, NY (US);

Dallas Lea, Niskayuna, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/3205 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823456 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/32055 (2013.01); H01L 21/32139 (2013.01); H01L 29/66545 (2013.01);
Abstract

Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.


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