The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

May. 29, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hiroyuki Miyazoe, White Plains, NY (US);

Cheng-Wei Cheng, White Plains, NY (US);

Sanghoon Lee, Mohegan Lake, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C30B 29/40 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); C30B 25/04 (2006.01); C30B 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02645 (2013.01); C30B 25/04 (2013.01); C30B 25/18 (2013.01); C30B 29/40 (2013.01); H01L 21/0228 (2013.01); H01L 21/02181 (2013.01); H01L 21/02546 (2013.01); H01L 21/02603 (2013.01); H01L 21/31122 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66522 (2013.01); H01L 29/66742 (2013.01); H01L 29/78681 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.


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