The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Sep. 09, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Tomonori Takahashi, Yokohama, JP;

Masanobu Shirakawa, Chigasaki, JP;

Osamu Torii, Tokyo, JP;

Marie Takada, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.


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