The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2021
Filed:
Apr. 30, 2020
Cadence Design Systems, Inc., San Jose, CA (US);
Cadence Design Systems Inc., San Jose, CA (US);
Abstract
The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.