The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Dec. 12, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bing Zhu, Shanghai, CN;

Kai Wang, Shanghai, CN;

Peng Zou, Shanghai, CN;

Fangjian Zhong, Shanghai, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/455 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/30076 (2013.01); G06F 9/30189 (2013.01); G06F 9/45533 (2013.01); G06F 2009/45566 (2013.01); G06F 2009/45583 (2013.01);
Abstract

A processing system includes a first register to store an invalidation mode flag associated with a virtual processor identifier (VPID) and a processing core, communicatively coupled to the first register, the processing core comprising a logic circuit to execute a virtual machine monitor (VMM) environment, the VMM environment comprising a root mode VMM supporting a non-root mode VMM, the non-root mode VMM to execute a virtual machine (VM) identified by the VPID, the logic circuit further comprising an invalidation circuit to execute a virtual processor invalidation (INVVPID) instruction issued by the non-root mode VMM, the INVVPID instruction comprising a reference to an INVVPID descriptor that specifies a linear address and the VPID and responsive to determining that the invalidation mode flag is set, invalidate, without triggering a VM exit event, a memory address mapping associated with the linear address.


Find Patent Forward Citations

Loading…