The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2021
Filed:
Jun. 29, 2018
Intel Corporation, Santa Clara, CA (US);
Fangfei Liu, Hillsboro, OR (US);
Bin Xing, Hillsboro, OR (US);
Michael Steiner, Hillsboro, OR (US);
Mona Vij, Hillsboro, OR (US);
Carlos Rozas, Portland, OR (US);
Francis McKeen, Portland, OR (US);
Meltem Ozsoy, Hillsboro, OR (US);
Matthew Fernandez, Portland, OR (US);
Krystof Zmudzinski, Forest Grove, OR (US);
Mark Shanahan, Raleigh, NC (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.