The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Sep. 27, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Takashi Ishihara, Machida, JP;

Wataru Nobehara, Sagamihara, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 27/105 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5222 (2013.01); H01L 24/09 (2013.01); H01L 27/0266 (2013.01); H01L 27/0292 (2013.01); H01L 27/105 (2013.01); H01L 2224/02331 (2013.01);
Abstract

A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL).


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