The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Aug. 30, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Smic New Technology Research and Development (Shanghai) Corporation, Shanghai, CN;

Inventor:

Fei Zhou, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/8238 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 21/3065 (2006.01); H01L 21/3213 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/28008 (2013.01); H01L 21/3065 (2013.01); H01L 21/32135 (2013.01); H01L 21/76224 (2013.01); H01L 21/76232 (2013.01); H01L 21/823481 (2013.01); H01L 29/66795 (2013.01);
Abstract

Semiconductor device and fabrication method are provided. The method includes: providing a semiconductor substrate; forming initial fins on the semiconductor substrate; forming a gate structure material layer on the semiconductor substrate and the initial fins, the gate material layer having a top surface higher than the initial fins; forming a trench in the gate structure material layer and the initial fins, which passes through the initial fins along a direction perpendicular to an extending direction of initial fins and in parallel with a surface of the semiconductor substrate to form initial fins into fins; forming an isolation layer in the trench having a top surface higher than the fins; and forming gate structures on both sides of the isolation layer by etching the gate structure material layer.


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Zhou, Fei. (2021). Fabrication method for fin-based semiconductor device (U.S. Patent No. 10916479). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10916479

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