The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Jan. 10, 2017
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Yohei Yamazawa, Yamanashi, JP;

Atsuki Furuya, Yamanashi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 16/00 (2006.01); H01L 21/306 (2006.01); H01J 37/32 (2006.01); C23C 16/509 (2006.01); C23C 16/455 (2006.01); C23C 16/52 (2006.01); H05H 1/46 (2006.01);
U.S. Cl.
CPC ...
H01J 37/32183 (2013.01); C23C 16/45536 (2013.01); C23C 16/45546 (2013.01); C23C 16/509 (2013.01); C23C 16/52 (2013.01); H01J 37/32 (2013.01); H01J 37/32458 (2013.01); H05H 1/46 (2013.01); H05H 2001/4682 (2013.01);
Abstract

A plasma processing apparatus includes a processing chamber, a high frequency power supply and a load variation stabilization circuit. The high frequency power supply is configured to supply a high frequency power to the processing chamber and generate plasma inside the processing chamber. The load variation stabilization circuit is connected in parallel with the processing chamber at a connection portion provided between the high frequency power supply and the processing chamber. The load variation stabilization circuit is configured to suppress variation in a load impedance when viewing a downstream side from the connection portion.


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