The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

May. 07, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kunal A. Khochare, Folsom, CA (US);

Camille C. Raad, Folsom, CA (US);

Richard P. Mangold, Forest Grove, OR (US);

Shachi K. Thakkar, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0866 (2016.01); G06F 11/16 (2006.01); G06F 11/00 (2006.01); G06F 12/0888 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0685 (2013.01); G06F 3/0688 (2013.01); G06F 11/00 (2013.01); G06F 11/1612 (2013.01); G06F 12/0238 (2013.01); G06F 12/0246 (2013.01); G06F 12/0866 (2013.01); G06F 12/0888 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7203 (2013.01); G06F 2212/7208 (2013.01); Y02D 10/00 (2018.01);
Abstract

Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.


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