The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Jan. 15, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Rohit Shetty, San Diego, CA (US);

Chiew-Guan Tan, San Diego, CA (US);

Gregory Lynch, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 19/00 (2006.01); H03K 3/356 (2006.01); H03K 3/012 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00315 (2013.01); H03K 3/012 (2013.01); H03K 3/35613 (2013.01); H03K 19/0013 (2013.01); H03K 19/018528 (2013.01);
Abstract

Certain aspects of the present disclosure generally relate to a level-shifting circuit. The level-shifting circuit generally includes a first pull-up path having at least one first diode and at least one first transistor, and a second pull-up path having at least one second diode and at least one second transistor. The level-shifting circuit may also include a first pull-down path having a third transistor and a fourth transistor, wherein the fourth transistor is coupled between the third transistor and the first diode; a second pull-down path having a fifth transistor and a sixth transistor, wherein the sixth transistor is coupled between the fifth transistor and the second diode; and an overvoltage protection circuit coupled to gates of the fourth transistor and the sixth transistor.


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