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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10910552 B1

PDFFull Text
Date of Patent:
Feb. 02, 2021

Filed:

Mar. 14, 2019

Magnetic memory device, method for manufacturing the same, and substrate treating apparatus

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Joonmyoung Lee, Anyang-si, KR;

Yong Sung Park, Suwon-si, KR;

Jeong-Heon Park, Hwaseong-si, KR;

Hyun Cho, Changwon-si, KR;

Ung Hwan Pi, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Lee IP Law, P.C.

Primary Examiner:

Dao H Nguyen

Int. Cl.
CPC ...
H01L 43/02 (2006.01); H01L 43/10 (2006.01); H01L 21/67 (2006.01); G11C 14/00 (2006.01); H01L 43/12 (2006.01); H01L 27/108 (2006.01); H01L 27/22 (2006.01); H01L 27/11 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); G11C 14/0036 (2013.01); G11C 14/0081 (2013.01); H01L 21/67155 (2013.01); H01L 27/224 (2013.01); H01L 27/226 (2013.01); H01L 43/10 (2013.01); H01L 43/12 (2013.01); G11C 11/161 (2013.01); H01L 27/108 (2013.01); H01L 27/11 (2013.01);
Abstract

A magnetic memory device, a method for manufacturing a magnetic memory device, and a substrate treating apparatus, the device including a substrate including a first memory region and a second memory region; a first magnetic tunnel junction pattern on the first memory region, the first magnetic tunnel junction pattern including a first free pattern and a first oxide pattern on the first free pattern; and a second magnetic tunnel junction pattern on the second memory region, the second magnetic tunnel junction pattern including a second free pattern and a second oxide pattern on the second free pattern, wherein a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

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