The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Aug. 07, 2019
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Sheng-Mou Lin, Hsin-Chu, TW;

Wen-Chou Wu, Hsin-Chu, TW;

Hsing-Chih Liu, Hsin-Chu, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 23/3128 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/18 (2013.01); H01L 2924/1421 (2013.01);
Abstract

The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.


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