The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Mar. 15, 2018
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Herb He Huang, Shanghai, CN;

Haiting Li, Shanghai, CN;

Jiguang Zhu, Shanghai, CN;

Clifford Ian Drowley, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/683 (2006.01); H01L 21/304 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/26506 (2013.01); H01L 21/26513 (2013.01); H01L 21/304 (2013.01); H01L 21/3046 (2013.01); H01L 21/30604 (2013.01); H01L 21/30608 (2013.01); H01L 21/30625 (2013.01); H01L 21/31133 (2013.01); H01L 21/6835 (2013.01); H01L 21/76224 (2013.01); H01L 21/76898 (2013.01); H01L 21/84 (2013.01); H01L 23/481 (2013.01); H01L 27/12 (2013.01); H01L 29/0649 (2013.01); H01L 29/78 (2013.01); H01L 27/088 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes a first substrate having a first surface and a second surface opposite to the first surface, a shallow trench isolation in the first substrate, the shallow trench isolation having a first depth, the first depth being a distance from a bottom of the shallow trench isolation to the first surface of the first substrate, a transistor on the first surface of the first substrate, a first dielectric cap layer covering the first surface of the first substrate, a first interconnect structure on the first dielectric cap layer, a carrier substrate bonded to the first substrate through the first dielectric cap layer, a second dielectric cap layer on the second surface of the first substrate; and a through silicon via extending through the second dielectric cap layer, the shallow trench isolation, and the first dielectric cap layer, and connected to the first interconnect structure.


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