The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2021
Filed:
Mar. 11, 2019
Applicant:
Toshiba Memory Corporation, Minato-ku, JP;
Inventors:
Tsukasa Tokutomi, Kamakura, JP;
Masanobu Shirakawa, Chigasaki, JP;
Marie Takada, Yokohama, JP;
Shohei Asami, Fujisawa, JP;
Masamichi Fujiwara, Kawasaki, JP;
Assignee:
TOSHIBA MEMORY CORPORATION, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/04 (2006.01); G06F 3/06 (2006.01); G11C 16/08 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 11/5671 (2013.01); G11C 16/08 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01);
Abstract
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.