The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2021
Filed:
Nov. 08, 2019
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Abstract
Systems, methods, and devices are described herein for a deterministic approach that includes receiving an original layout of a semiconductor device that has a number of layers. A violation of a first design rule associated with a first layer of the number of layers is identified. A design rule compilation includes a plurality of design rules associated with each layer of the number of layers. A plurality of derived layers are generated based upon the plurality of design rules. Each derived layer of the plurality of derived layers includes one or more layers of the number of layers of the semiconductor device in which a physical movement to one layer impacts another layer. A forbidden region associated with a second layer of the plurality of layers is designated. A new layout of the number of layers having oriented differently than the original layout is generated such that no layer protrudes within the forbidden region.