The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Feb. 07, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Pascal Meinerzhagen, Hillsboro, OR (US);

Stephen Kim, Hillsboro, OR (US);

Dongmin Yoon, Ann Arbor, MI (US);

Minki Cho, Hillsboro, OR (US);

Muhammad Khellah, Tigard, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G05F 1/563 (2006.01); G05F 1/59 (2006.01); G06F 1/3296 (2019.01); G06F 1/3287 (2019.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G05F 1/563 (2013.01); G05F 1/59 (2013.01); G06F 1/324 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01);
Abstract

An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.


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