The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Sep. 17, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Sheng-Chieh Chen, Taichung, TW;

Ming-Chyi Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/1157 (2017.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 27/1157 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/66795 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

A process is provided to fabricate a finFET device. A gate electrode layer is positioned over a dielectric layer. The gate electrode layer and the dielectric layer are both positioned over and surrounding a fin-shaped semiconductor structure. A gate electrode is formed from the gate electrode layer through a two-step patterning process. At a first patterning step, an upper portion of the gate electrode layer is patterned. Then a dielectric film is formed covering the patterned upper portion of the gate electrode layer. After the dielectric film is formed, a second patterning process is performed to pattern a lower portion of gate electrode layer.


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