The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

May. 10, 2019
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Gaspard Hiblot, Heverlee, BE;

Sylvain Baudot, Woluwe Saint-Pierre, BE;

Hans Mertens, Leuven, BE;

Julien Jussot, Kessel-Lo, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/775 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66553 (2013.01); H01L 21/02134 (2013.01); H01L 21/02164 (2013.01); H01L 21/02282 (2013.01); H01L 21/02348 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.


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