The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Jun. 03, 2019
Applicant:

Longitude Flash Memory Solutions Ltd., Dublin, IE;

Inventors:

Igor Polishchuk, Fremont, CA (US);

Sagy Charel Levy, Zichron Yaakov, IL;

Krishnaswarny Ramkumar, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 29/00 (2006.01); G11C 16/04 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); H01L 27/11526 (2017.01); H01L 27/11563 (2017.01); H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 29/4234 (2013.01); B82Y 10/00 (2013.01); G11C 16/0466 (2013.01); H01L 21/0214 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 27/11526 (2013.01); H01L 27/11563 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 29/0649 (2013.01); H01L 29/0676 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/4916 (2013.01); H01L 29/511 (2013.01); H01L 29/512 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66795 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01);
Abstract

An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.


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