The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Apr. 25, 2019
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Ting-Yao Lin, Hsinchu County, TW;

Chun Chiang, Hsinchu, TW;

Ping-Chen Chang, Pingtung County, TW;

Tien-Hao Tang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/74 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0262 (2013.01); H01L 29/66371 (2013.01); H01L 29/7408 (2013.01);
Abstract

A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.


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