The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2021
Filed:
Jul. 05, 2019
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Sang Hwan Kim, Seoul, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/10 (2006.01); G11C 8/18 (2006.01); G11C 8/06 (2006.01); G06F 12/02 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G06F 12/0888 (2016.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 8/10 (2013.01); G06F 12/0246 (2013.01); G06F 12/0888 (2013.01); G11C 7/12 (2013.01); G11C 7/222 (2013.01); G11C 8/06 (2013.01); G11C 8/18 (2013.01); G11C 29/4401 (2013.01);
Abstract
A semiconductor memory device includes a memory cell array, a buffer unit, control logic, and a decoding circuit. The memory cell array includes a plurality of memory cells. The buffer coupled to the memory cell array, and includes a first memory area, a second memory area, and a conversion memory area. The control logic outputs a mode control signal representing an operating mode of the buffer. The decoding circuit controls the operating mode of the buffer such that the conversion memory area operates as any one of a main memory area and a repair memory area, based on the mode control signal.