The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Apr. 26, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Eric Robert Trumbauer, Celina, TX (US);

Brant William Paquette, Allen, TX (US);

Vince Christian Samek, Richmond, VA (US);

Michael Jay Jenson, Richardson, TX (US);

David Matthew Curran, Plano, TX (US);

Jon Evan Button, Dallas, TX (US);

Charles David Gordon, McKinney, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); G06T 7/00 (2017.01); G06T 7/70 (2017.01);
U.S. Cl.
CPC ...
G06T 7/0004 (2013.01); G06T 7/001 (2013.01); G06T 7/70 (2017.01); G06T 2207/30148 (2013.01);
Abstract

A method of providing a semiconductor device and a computer-readable medium having instructions for performing the method are disclosed. The method includes receiving a first wafer defect map that defines comparison regions and identifies visual defect locations for a wafer. A format of the comparison regions is determined, with the format chosen from a group including die-to-die, partial-shot-to-partial-shot and full-shot-to-full-shot. If the comparison format is not die-to-die, mapping information is received that provides die locations within the comparison regions. A wafer layout map is provided that identifies die locations within the wafer.


Find Patent Forward Citations

Loading…