The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2021
Filed:
Feb. 01, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Lakshminarayana Pappu, Folsom, CA (US);
Amit Kumar Srivastava, Folsom, CA (US);
Robert Milstrey, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/30 (2006.01); G01R 31/28 (2006.01); G06F 11/26 (2006.01); G01R 31/3183 (2006.01); G01R 31/317 (2006.01); G06F 30/3323 (2020.01); G06F 11/27 (2006.01); G06F 30/20 (2020.01); G06F 11/30 (2006.01); G06F 30/333 (2020.01);
U.S. Cl.
CPC ...
G01R 31/31835 (2013.01); G01R 31/2853 (2013.01); G01R 31/31703 (2013.01); G01R 31/318307 (2013.01); G06F 11/26 (2013.01); G06F 11/27 (2013.01); G06F 11/30 (2013.01); G06F 30/20 (2020.01); G06F 30/333 (2020.01); G06F 30/3323 (2020.01);
Abstract
Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for in-field safety tests on system-level and circuit-level, providing real-time and on-chip tests with respect to, including but not limited to, circuit reliability, power consumption, and system safety. The in-field safety tests may include implementing voltage droop monitors (VDMs) and signature collectors with authentication-enabled launching. Other embodiments may be described and claimed.