The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2021

Filed:

Oct. 17, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brent A. Anderson, Jericho, VA (US);

Steven Bentley, Menands, NY (US);

Su Chen Fan, Cohoes, NY (US);

Balasubramanian Pranatharthiharan, Watervliet, NY (US);

Junli Wang, Slingerlands, NY (US);

Ruilong Xie, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66666 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/41741 (2013.01); H01L 29/6656 (2013.01); H01L 29/7827 (2013.01); H01L 29/665 (2013.01);
Abstract

Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.


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