The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2021
Filed:
Apr. 03, 2019
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventors:
Hsu-Chi Cho, Zhubei, TW;
Cheng-Ta Yang, Kaohsiung, TW;
Assignee:
WINBOND ELECTRONICS CORP., Taichung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11521 (2017.01); H01L 29/66 (2006.01); H01L 21/3115 (2006.01); H01L 21/3215 (2006.01); H01L 21/3205 (2006.01); H01L 29/49 (2006.01); H01L 29/40 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 27/11531 (2017.01); H01L 27/11558 (2017.01); H01L 27/11526 (2017.01); H01L 27/115 (2017.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/3115 (2013.01); H01L 21/31111 (2013.01); H01L 21/31155 (2013.01); H01L 21/32053 (2013.01); H01L 21/32155 (2013.01); H01L 27/115 (2013.01); H01L 27/11526 (2013.01); H01L 27/11531 (2013.01); H01L 27/11558 (2013.01); H01L 29/401 (2013.01); H01L 29/40114 (2019.08); H01L 29/4933 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract
A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.