The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2021

Filed:

Oct. 02, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Wei Zhou, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/20 (2006.01); B23K 20/02 (2006.01);
U.S. Cl.
CPC ...
H01L 24/95 (2013.01); B23K 20/023 (2013.01); H01L 21/2007 (2013.01); H01L 24/14 (2013.01); H01L 24/81 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81815 (2013.01); H05K 2203/0475 (2013.01);
Abstract

Methods of fabricating semiconductor device packages may involve forming trenches in a first wafer. A dielectric material may be placed over a first active surface. Electrically conductive elements may be operatively connected to bond pads of a second wafer with the dielectric material interposed between the first wafer and the second wafer. Force may be applied to the first wafer and the second wafer while exposing the first wafer and the second wafer to an elevated temperature. Portions of the dielectric material may flow into the trenches. The elevated temperature may be reduced to at least partially solidify the dielectric material. A thickness of the first wafer may be reduced to reveal the portions of the dielectric material in the trenches. The first wager may be singulated and the second wafer may be singulated to form semiconductor dice.


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