The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2021
Filed:
Mar. 02, 2018
Applicant:
Intel Ip Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel IP Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 27/40 (2006.01); H01G 4/30 (2006.01); H01G 4/005 (2006.01); H01G 4/40 (2006.01); H01F 41/04 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01F 27/28 (2006.01); H01L 23/532 (2006.01); H03B 5/08 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/288 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01F 27/40 (2013.01); H01F 27/2804 (2013.01); H01F 41/041 (2013.01); H01G 4/005 (2013.01); H01G 4/30 (2013.01); H01G 4/40 (2013.01); H01L 23/528 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 21/02164 (2013.01); H01L 21/02203 (2013.01); H01L 21/02274 (2013.01); H01L 21/2885 (2013.01); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5329 (2013.01); H01L 23/53228 (2013.01); H03B 5/08 (2013.01);
Abstract
A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.