The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2021
Filed:
Nov. 16, 2018
International Business Machines Corporation, Armonk, NY (US);
Karthik V. Swaminathan, Mount Kisco, NY (US);
Ramon Bertran Monfort, New York, NY (US);
Alper Buyuktosunoglu, White Plains, NY (US);
Pradip Bose, Yorktown Heights, NY (US);
Nandhini Chandramoorthy, Yorktown Heights, NY (US);
Chen-Yong Cher, Port Chester, NY (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (V), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.