The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Mar. 28, 2019
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

William E. Edwards, Washtenaw, MI (US);

John M. Pigott, Phoenix, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H02H 1/00 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
H02H 9/04 (2013.01); H02H 1/0007 (2013.01); H02H 9/046 (2013.01); H03K 19/017509 (2013.01);
Abstract

An input protection circuit () and associated method are disclosed for protecting a circuit input (V) from positive and negative overvoltages at an input voltage (V) with a high-voltage PMOSFET (P) having a gate, a drain connected across a zener diode (ZD) to the gate, and a source connected to receive an input voltage; a blocking FET (N) having a gate connected to a power supply voltage, a drain connected across a zener diode (ZD) to the power supply voltage, and a source connected to the gate of the high-voltage PMOSFET; a high-voltage NMOSFET (N) having a gate connected to the power supply voltage, a source providing the protected output voltage and connected across a zener diode (ZD) to the gate, and a drain connected to a source follower node and a level shifter circuit () connected between the drain of the high-voltage PMOSFET and the source follower node.


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