The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Jun. 18, 2019
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Shigenori Kido, Tokyo, JP;

Hidenori Fujii, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0878 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01); H01L 29/0692 (2013.01); H01L 29/456 (2013.01); H01L 29/4908 (2013.01); H01L 29/66893 (2013.01); H01L 29/7801 (2013.01);
Abstract

The semiconductor device includes: an epitaxial layer of a first conductivity type formed on a first principal surface of a semiconductor substrate; a first semiconductor region of the first conductivity type formed from an outermost surface to an inner portion of the epitaxial layer; and a third semiconductor region of a second conductivity type formed from a bottom surface of the first semiconductor region to an inner portion of the semiconductor substrate. The method includes: (a) polishing a second principal surface opposite to the first principal surface of the semiconductor substrate above which at least a source region, a drain region, and a gate electrode are formed to thin the substrate; and (b) ion-implanting impurities of the second conductivity type from the second principal surface of the polished semiconductor substrate to form the third semiconductor region.


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