The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Feb. 08, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hoi Sung Chung, Suwon-si, KR;

Tae Sung Kang, Seoul, KR;

Dong Suk Shin, Yongin-si, KR;

Kong Soo Lee, Hwaseong-si, KR;

Jun-Won Lee, Asan-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 27/108 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/51 (2006.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 21/266 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10873 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02667 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/31111 (2013.01); H01L 21/324 (2013.01); H01L 21/76897 (2013.01); H01L 27/10855 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/518 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/045 (2013.01);
Abstract

Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.


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