The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Jul. 03, 2019
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Chin-Hsiung Hsu, Hsinchu, TW;

Philip Hui-Yuh Tai, Mountain View, CA (US);

Sheng-Wei Yang, Hsinchu, TW;

Guo-Ting Wang, Hsinchu, TW;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 16/901 (2019.01); G06F 21/60 (2013.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 16/9024 (2019.01); G06F 21/602 (2013.01);
Abstract

In an example embodiment, a computer-implemented method is provided for receiving an integrated circuit design, wherein the integrated circuit design comprises at least one position in violation of one or more design rules associated with the integrated design, identifying one or more design patterns at the at least one violating position, generating one or more pattern graphs for the one or more design patterns, extracting a system on chip design for transformation into a block graph, and. comparing the block graph with each of the one or more pattern graphs to determine whether the at least one violating position is cleared. In circumstances where a match is found between the block graph and the each of the one or more pattern graphs, the computer-implemented method further comprises changing the one or more design patterns and repeating the step of comparing until there is no further match found.


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