The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Sep. 26, 2016
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Georgios Yorgos Palaskas, Portland, OR (US);

Paolo Madoglio, Beaverton, OR (US);

Dirk Friedrich, Munich, DE;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 19/12 (2006.01); H03C 5/00 (2006.01); H03M 1/86 (2006.01); H04B 1/04 (2006.01); H03C 3/09 (2006.01);
U.S. Cl.
CPC ...
H03B 19/12 (2013.01); H03C 3/0908 (2013.01); H03C 3/0916 (2013.01); H03C 5/00 (2013.01); H03M 1/86 (2013.01); H04B 1/0475 (2013.01);
Abstract

Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.


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