The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Jan. 07, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventor:

Shuai Guo, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); B81C 3/00 (2006.01); H01L 21/66 (2006.01); H01L 23/544 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); B81C 3/004 (2013.01); H01L 22/20 (2013.01); H01L 23/544 (2013.01); H01L 25/50 (2013.01); H01L 2223/54426 (2013.01); H01L 2225/06593 (2013.01);
Abstract

Embodiments of methods and systems for wafer bonding alignment compensation are disclosed. The method comprises bonding a first pair of wafers including a first wafer and a second wafer, wherein the first pair of wafers have a plurality of corresponding bonding alignment mark pairs each including a first bonding alignment mark on the first wafer and a second bonding alignment mark on the second wafer; measuring alignment positions of the plurality of bonding alignment mark pairs; determining a mean run-out misalignment between the first pair of wafers using the alignment measurement, wherein the mean run-out misalignment indicates a deformation of at least one of the first pair of wafers; and during bonding of a second pair of wafers, controlling a wafer deformation adjustment module to compensate for the run-out misalignment based on the mean run-out misalignment of the first pair of wafers.


Find Patent Forward Citations

Guo, Shuai. (2021). Methods and systems for wafer bonding alignment compensation (U.S. Patent No. 10886256). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10886256

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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