The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Aug. 30, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Smic New Technology Research and Development (Shanghai) Corporation, Shanghai, CN;

Inventor:

Fei Zhou, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01); H01L 21/027 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/0273 (2013.01); H01L 21/02164 (2013.01); H01L 21/02208 (2013.01); H01L 21/02274 (2013.01); H01L 21/31053 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 21/02219 (2013.01); H01L 21/02271 (2013.01);
Abstract

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate. The base substrate includes a plurality of non-device regions. The method also includes forming a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions. In addition, the method includes forming a first barrier layer on sidewalls of the edge fin. Further, the method includes forming an isolation material layer over the base substrate, over a top of the edge fin, over sidewall and top surfaces of the middle fin structure, and over sidewalls of the first barrier layer. The isolation material layer has a material density smaller than the first barrier layer.


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Zhou, Fei. (2021). Semiconductor structure and fabrication method thereof (U.S. Patent No. 10886179). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10886179

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