The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2021
Filed:
Mar. 27, 2020
Applicant:
Ambiq Micro, Inc., Austin, TX (US);
Inventors:
Christophe J. Chevallier, Palo Alto, CA (US);
Stephen James Sheafor, Boulder, CO (US);
Assignee:
AMBIQ MICRO, INC., Austin, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/412 (2006.01); G11C 15/04 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G06F 11/10 (2006.01); G11C 29/50 (2006.01); G11C 11/419 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4125 (2013.01); G06F 11/1048 (2013.01); G11C 11/5621 (2013.01); G11C 15/043 (2013.01); G11C 15/046 (2013.01); G11C 16/3459 (2013.01); G11C 29/50 (2013.01); G11C 29/50016 (2013.01); G11C 11/419 (2013.01); G11C 2029/0411 (2013.01);
Abstract
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.