The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Aug. 30, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bikram Baidya, Portland, OR (US);

John A. Swanson, Forest Grove, OR (US);

Kumara Sastry, Hillsboro, OR (US);

Prasad N. Atkar, Portland, OR (US);

Vivek K. Singh, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/398 (2020.01); G06F 17/18 (2006.01); G06N 5/02 (2006.01); G06K 9/62 (2006.01); G06F 30/392 (2020.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 17/18 (2013.01); G06F 30/392 (2020.01); G06K 9/6232 (2013.01); G06N 5/022 (2013.01); G06N 20/00 (2019.01);
Abstract

An improved random forest model is provided, which has been trained based on silicon data generated from tests of previously fabricated chips. An input is provided to the random forest model, the input including a feature set of a pattern within a particular chip layout, the feature set identifying geometric attributes of polygonal elements within the pattern. A result is generated by the random forest model based on the input, where the result identifies a predicted attribute of the pattern based on the silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, where the previously fabricated chips have chip layouts are different from the particular chip layout.


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