The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Dec. 20, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young-Hun Seo, Hwaseong-si, KR;

Kwang-Il Park, Yongin-si, KR;

Seung-Jun Bae, Hwaseong-si, KR;

Sang-Uhn Cha, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 11/4093 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/1048 (2013.01); G11C 11/4093 (2013.01); G11C 29/52 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.


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