Fast parallel crc determination to support ssd testing

Abstract

Fast parallel CRC determination to support SSD testing includes a test data pattern generator for generating test data for storage onto a memory storage device under test (DUT), wherein the generator is operable to generate, every clock cycle, a respective N bit word comprising a plurality of M bit subwords, a digest circuit operable to employ a digest function on each N bit word to produce, every clock cycle, a respective word digest for each N bit word, and a storage circuit operable to store each N bit word along with an associated word digest to the DUT. The digest circuit includes a plurality of first circuits each operable to perform a first digest function on a respective subword of the plurality of subwords, in parallel, to produce a plurality of subword digests, a plurality of second circuits each operable to perform a second digest function on a respective subword digest of the plurality of subword digests, the second digest function being equivalent to shifting the respective subword digest through a linear feedback shift register (LFSR) then followed by (I×M) zero bits, wherein I is related to a word position, within the N bit word, of a respective subword that generated the respective subword digest, and an XOR circuit operable to XOR outputs of the plurality of second circuits together along with a shifted prior LFSR state to produce the word digest of the N bit word.