The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Jul. 01, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Georges Manuel Faure Vaquero, Heredia, CR;

John Cruz Mejia, Hillsboro, OR (US);

Scott M. Rider, Beaverton, OR (US);

David M. Lee, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 9/4401 (2018.01); G06F 11/14 (2006.01); G06F 11/30 (2006.01); G06F 11/07 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4413 (2013.01); G06F 11/0736 (2013.01); G06F 11/0745 (2013.01); G06F 11/0793 (2013.01); G06F 11/1417 (2013.01); G06F 11/3041 (2013.01); G06F 11/3051 (2013.01); G06F 11/3055 (2013.01); G06F 13/00 (2013.01);
Abstract

Aspects of the embodiments are directed to propagating an in-band hot reset through an add-in card compliant with a peripheral component interconnect express (PCIe) protocol. A host system can transmit an in-band hot reset to the add-in card across a link compliant with the PCIe protocol. A non-transparent bridge (NTB) on the add-in card can receive the in-band hot reset and reset configuration registers on the NTB. A system management controller can poll the NTB register values to determine that the polled configuration registers are different from expected values stored on an electrically erasable programmable random access memory (EEPROM). The SMC can signal a warm reset to a peripheral component based on the determination that the polled configuration register value is different from the expected register value.


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