The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2021
Filed:
May. 04, 2018
Applicant:
Rambus Inc., Sunnyvale, CA (US);
Inventor:
Stephen G. Tell, Chapel Hill, NC (US);
Assignee:
RAMBUS INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 13/40 (2006.01); G06F 1/26 (2006.01); H04L 7/02 (2006.01); G06F 1/10 (2006.01); G06F 13/38 (2006.01); G11C 7/10 (2006.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/10 (2013.01); G06F 12/0246 (2013.01); G06F 13/382 (2013.01); G06F 13/4072 (2013.01); G11C 7/1072 (2013.01); H03K 19/1776 (2013.01); H04L 7/02 (2013.01); G06F 2212/7201 (2013.01);
Abstract
Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.