The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jul. 16, 2020
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Andrew Ho, San Jose, CA (US);

Vladimir Stojanovic, Lexington, MA (US);

Bruno W. Garlepp, Sunnyvale, CA (US);

Fred F. Chen, San Francisco, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 17/29 (2015.01); H04L 1/20 (2006.01); H04L 1/24 (2006.01); H04L 25/03 (2006.01); H04B 17/21 (2015.01); G01R 31/317 (2006.01); H04L 27/01 (2006.01); H04L 7/033 (2006.01); G06F 11/08 (2006.01); H04L 7/04 (2006.01); H04L 7/10 (2006.01);
U.S. Cl.
CPC ...
H04B 17/29 (2015.01); G01R 31/31711 (2013.01); G06F 11/08 (2013.01); H04B 17/21 (2015.01); H04L 1/20 (2013.01); H04L 1/241 (2013.01); H04L 1/242 (2013.01); H04L 7/033 (2013.01); H04L 25/03006 (2013.01); H04L 25/03057 (2013.01); H04L 25/03949 (2013.01); H04L 27/01 (2013.01); H04L 7/043 (2013.01); H04L 7/10 (2013.01); H04L 25/03146 (2013.01);
Abstract

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.


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