The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Aug. 31, 2017
Applicant:

Csmc Technologies Fab2 Co., Ltd., Jiangsu, CN;

Inventors:

Yan Gu, Jiangsu, CN;

Shikang Cheng, Jiangsu, CN;

Sen Zhang, Jiangsu, CN;

Assignee:

CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi New District, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 27/06 (2006.01); H01L 27/098 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7803 (2013.01); H01L 27/02 (2013.01); H01L 27/06 (2013.01); H01L 27/098 (2013.01); H01L 29/06 (2013.01); H01L 29/66712 (2013.01);
Abstract

A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain () having a first conduction type; and a first conduction type region () disposed on a front face of the drain; the JFET region further includes: a JFET source () having a first conduction type; a first well () having a second conduction type; a metal electrode () formed on the JFET source (), which is in contact with the JFET source (); a JFET metal gate () disposed on the first well () at both sides of the JFET source (); and a first clamping region () located below the JFET metal gate () and within the first well ().


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