The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Apr. 29, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chien-Hung Lin, Hsin-Chu, TW;

Chun-Chieh Mo, Kaohsiung, TW;

Shih-Chi Kuo, Yangmei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 29/06 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66833 (2013.01); H01L 21/31144 (2013.01); H01L 21/32137 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 29/0649 (2013.01); H01L 29/42344 (2013.01); H01L 29/792 (2013.01);
Abstract

A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.


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